1. Field of the Invention
The present invention relates generally to automatic frequency control circuit (referred to as AFC circuit hereinafter) having a reduced synchronization capturing period, and more particularly, to an AFC circuit suitable for use in, for example, a chrominance signal processing circuit in a recording system of a video tape recorder (referred to as VTR hereinafter).
2. Description of the Background Art
Conventionally, a chrominance signal processing circuit for a VTR is constituted such that a carrier chrominance signal having a frequency of 3.58 MHz is converted into a low-frequency converted chrominance signal having a frequency f.sub.a of 629 kHz and recorded on a magnetic tape at the time of recording, and at the time of reproducing, the low-frequency converted chrominance signal reproduced from the magnetic tape is converted into a reproduced carrier chrominance signal having a frequency f.sub.c of 3.58 MHz. Such a method of recording chrominance signals can prevent a frequency bandwidth required for recording from being enlarged.
A frequency conversion of a carrier chrominance signal into a low-frequency converted chrominance signal at a time of recording is generally performed based on an output signal obtained from a voltage controlled oscillation circuit (referred to as VCO hereinafter) as a result of controlling an oscillating frequency of the VCO based on a horizontal synchronizing signal obtained separated from an input video signal, that is, as a result of an automatic frequency controlling. Namely, the above described frequency conversion of a chrominance signal is performed based on an oscillating frequency signal of a VCO circuit in an AFC circuit, captured into a frequency of a horizontal synchronizing signal and phase-locked therewith.
Meanwhile, such problems as follows occur in converting a frequency of a chrominance signal in response to a signal locked into a frequency of an inputted horizontal synchronizing signal by using a VCO circuit. More specifically, if the extent that an oscillating frequency of the VCO circuit changes is large, when the oscillating frequency of the VCO circuit and the frequency of the horizontal synchronizing signal are largely different, such as in activating an AFC circuit, it takes a long time to capture the oscillating frequency of the VCO circuit into the frequency of the horizontal synchronizing signal. On the other hand, it is difficult to reduce the extent that the oscillating frequency of the VCO circuit changes because of dispersion of parameters of the VCO circuit.
Therefore, in order to resolve such problems, a frequency converting circuit is proposed, in which loop gain of an AFC loop including a VCO circuit is increased during the fluctuation of a horizontal synchronizing signal and which is disclosed in, for example, Japanese Patent Laying Open No. 60-66590.
FIG. 1 is a schematic block diagram showing a conventional chrominance signal processing circuit including such a frequency converting circuit in a recording system of a VTR. Referring to FIG. 1, a carrier chrominance signal in a video signal to be recorded is applied to an input terminal 101 and is supplied to a bandpass filter 103 (referred to as BPF hereinafter) of 3.58 MHz. The carrier chrominance signal passed through the BPF 103 is supplied to an ACC amplifier 104 wherein an ACC level of the signal is fixed by an automatic chrominance control by means of an ACC loop comprising the ACC amplifier 104, a burst amplifier 105 and an ACC detector 106. An output of the ACC amplifier 104, after a burst level thereof is emphasized by 6dB by means of a burst amplifier circuit 107, is supplied to a main converter 108. The main converter 108 is a frequency converter for converting a carrier chrominance signal of 3.58 MHz into a low-frequency converted chrominance signal of 629 kHz, based on a carrier signal of 4.21 MHz supplied from a BPF 109. Such carrier signal of 4.21 MHz is supplied from a sub-converter 110 through the BPF 109. The sub-converter 110 generates such carrier signal of 4.21 MHz by multiplying a signal of 3.58 MHz which phase is locked into a sub-carrier signal of 3.58 MHz of an inputted chrominance signal of and a signal of 40f.sub.H (f.sub.H is a horizontal synchronizing signal frequency) which phase is locked into a horizontal synchronizing signal of an inputted video signal.
The signal of 3.58 MHz is generated by an APC loop comprising a VCO circuit 111 and a phase comparator circuit 112. More specifically, the VCO 111 has an oscillating frequency controlled by the phase comparator circuit 112 such that an oscillating signal thereof is phase-locked into a burst signal supplied from the burst amplifier 105.
On the other hand, a signal of 40f.sub.H supplied to the sub-converter 110 is obtained by converting a signal having a frequency of 320 f.sub.H supplied from an AFC circuit 113 into a signal having a frequency of 40 f.sub.H by means of a phase shift circuit 114. The AFC circuit 113 generates a signal of 320 f.sub.H which is phase-locked to a horizontal synchronizing signal H.sub.SYNC extracted from the inputted video signal and supplied through a terminal 119, as will be described later.
A killer circuit 116 is provided for eliminating chrominance signal components when a killer detection circuit 115 detects that a level of a chrominance signal in the inputted signal is decreased below a predetermined level due to various causes.
The chrominance signal which is low-frequency converted by the main converter 108 is outputted as a low-frequency converted chrominance signal of 629 kHz through a LPF 117 and a terminal 118 and then recorded on a magnetic tape by a magnetic head (not shown).
FIG. 2 is a block diagram showing in detail the AFC circuit 113 shown in FIG. 1, which is disclosed in, for example, the above described Japanese Patent Laying Open No. 60-66590. Referring to FIG. 2, an output signal of a VCO 1 oscillated at a frequency of a predetermined multiple of the horizontal synchronizing signal frequency f.sub.H is externally supplied from an output terminal 4 and also frequency-divided by a frequency-divider 2 and thereafter supplied to a phase comparing circuit 3. The horizontal synchronizing signal H.sub.SYNC supplied through the terminal 119 is also supplied to the phase comparing circuit 3. The phase comparing circuit 3 compares phases of both the signals to detect phase error therebetween and supplies the corresponding error output to an AFC current source 6 through an adder 8. A control current corresponding to the error output is supplied from the AFC current source 6, smoothed by a smoothing circuit 5 and then applied to a control input of the VCO 1. As a result, the VCO 1 oscillates stably in phase-synchronization with the horizontal synchronizing signal.
Now, it is assumed that the horizontal synchronizing signal period temporarily fluctuates greatly from this state. Then, as described above, a control signal for stabilizing the AFC loop is supplied from the phase comparing circuit 3 through the adder 8 to the AFC current source 6. At the same time, an AFCID circuit 7, on receiving an output of the frequency divider 2 and the horizontal synchronizing signal from the terminal 119, detects that the fluctuation of the horizontal synchronizing signal is significantly large and in response thereto, supplies an additional control signal to the adder circuit 8. The control signal is added to the above described control signal from the phase comparing circuit 3 in the adder 8, which is further supplied to the AFC current source 6. Thus, when the fluctuation of the horizontal synchronizing signal period is significantly large, a value of a control current supplied to the VCO 1 becomes large, so that the VCO 1 performs a frequency control more quickly. As the foregoing, in a conventional AFC circuit, in case fluctuation of a horizontal synchronizing signal period is significantly large, reduction of a capturing period of a AFC loop is achieved by temporarily increasing loop gain of the AFC loop.
Meanwhile, in case signals recorded on a video tape by a certain VTR are reproduced by another VTR, a phase of a horizontal synchronizing signal is shifted in a first period or a first horizontal synchronizing signal is dropped out at a timing of switching from the reproduction by a rotary head of A channel to the reproduction by a rotary head of B channel, that is, at a turning point of each field. More specifically, a tape width is changed due to tension of the tape caused when a rotary head is pressed onto the tape during the recording and reproducing and each VTR differs in tension of a tape, which results in fluctuation or dropout of a horizontal synchronizing signal at a turning point of each field, then reproduced by different VTRs. If this video signal including such a defective horizontal synchronizing signal in each field is recorded by still another VTR, in a AFC circuit in a chrominance signal processing circuit contained in the VTR, the AFC loop is disturbed every vertical period due to the above described detective horizontal synchronizing signal, causing the hue of the signal to be deteriorated. Since in such a case, defects such as fluctuation and dropout of the horizontal synchronizing signal occur only in the first horizontal period of each field, the above described deterioration of the hue can be prevented by correcting the defects in this first one period. If the above described AFC circuit shown in FIG. 2 is adopted in such a case, it detects a defective horizontal synchronizing signal in each field, thereby supplying a large AFC control current to the VCO and increasing the AFC loop gain, so that capturing operation is performed quickly. However, when such an excessive AFC current is supplied to the VCO, a large fluctuation of an oscillating frequency of the VCO continues after the first period in each field, thereby affecting the AFC loop even though it is in a normal state in which basically no correction is required, causing unnecessarily a phase to be unlocked and hue to be deteriorated.
Now, consider a case in which the received television broadcasting is directly recorded on a magnetic tape by using the AFC circuit of FIG. 2. In this case, if a horizontal synchronizing signal (including equalizing pulses) in a vertical synchronizing signal period fluctuates in a weak electric field while the AFC control current and the loop gain of the AFC loop are increased as described above, the noise in such a vertical synchronizing signal period is further increased by the increased loop gain, so that an AFC operation of the AFC loop is significantly disturbed since the noise during the vertical synchronizing signal period has higher level than that of the noise during a normal horizontal synchronizing signal period. That is, in such a case, the increase of the loop gain of the AFC loop causes the AFC loop to be disturbed and makes a capturing time period of the AFC loop longer, resulting in the deterioration of the hue in an upper region of a TV picture frame when the signals recorded on the tape in the above described manner are reproduced.